The present invention relates to electronics, and more particularly, to a method for making a dynamic random access memory (DRAM).
A DRAM includes a plurality of memory cells. Each DRAM cell defined by a bit line and a word line, includes a semiconductor/dielectric/semiconductor type capacitance to store binary data and a transistor operating as a switch. In an overlay type DRAM cell architecture, the capacitance is formed above the transistor between the word line and the bit line. Such an architecture is shown in FIG. 1.
More particularly, each DRAM cell comprises a MOS type access transistor 3 with N+ dopant implantations 4. A contact block 5 enables the contact between the transistor and the capacitance. The capacitance is produced by litho-etching by making a slot in the silicon oxide TEOS, thus forming a ring 6 for the capacitance. The capacitance is formed by a lower electrode elec 1 and an upper electrode elec 2. Both electrodes are separated by a dielectric 7. Another contact block 8 is used to make the contact between the bit line 2 and the transistor 3.
To increase the surface for the capacitance without increasing the size of the ring 6, the lower electrode elec 1 is deposited in the form of hemispherical polysilicon grains according to a hemispherical grain polysilicon (HSG) method. This method makes it possible to double the surface, and therefore, the capacitance. The capacitance C=xcex5*S/E, where E is the thickness of the dielectric, S the surface of the capacitance and E the dielectric constant.
However, in such an architecture, the size of the capacitance is limited by alignment tolerances which are necessary for the insertion of the bit line contact. Contact is prohibited between the capacitance and the bit line. In this way, when it is necessary to increase the integration density, i.e., to produce more memory cells in the same surface unit, the implementation of the contact 8 of the bit line becomes problematic. The corresponding explanation is given with reference to FIG. 2.
First of all, it is necessary to etch a wide opening 9 in the upper electrode plate elec 2 in the middle of the capacitance to insert the contact of the bit line 8. The photoetching step of the upper electrode uses a specific mask, which is referred to as elec 2 grid. This specific mask has very strict alignment constraints with respect to the alignment of an elec 1 grid mask used at the lower level to produce the opening of the capacitance.
A first alignment rule of the upper electrode elec 2 of the capacitance with respect to the lower electrode elec 1 must be observed. Photolithography technique limitations make it necessary to account for a minimum distance with reference as marked in FIG. 2, so that the electrode elec 2 never projects onto the electrode elec 1.
A preliminary step prior to the contact photoetching step includes depositing silicon oxide to fill the rings of the capacitances, and the opening produced in the upper electrode plate elec 2. The purpose of this step is to planarize the surface and prevent any contact between the capacitance and the bit line.
The next step includes etching the contact. This step requires the use of a specific contact mask referred to as a contact grid. The contact grid must also be perfectly aligned to be able to insert the contact at the center of the opening 9 previously produced in the electrode plate elec 2. This condition is imposed by the need to connect the contact 8 with a block 5 of the tungsten interconnection level which enables the contact with the transistor.
In addition, it is necessary to prevent the metal part of the contact 8 from coming into electrical contact with the upper electrode elec 2 of the capacitance. In this way, a second alignment rule of the contact with respect to the electrode plate elec 2 must be observed. This alignment rule makes it necessary to account for a minimum distance with the reference b as marked in FIG. 2 to protect the etching of the contact 8. This ensures that the dimensions of the contact grid are included in the dimensions of the elec 2 gird used to etch the opening of the electrode plate elec 2.
Therefore, the alignment rules that must be observed to produce the contact 8 of the bit line make it necessary to account for alignment margins a and b, respectively, which are specific to the limitations of the photolithography equipment used. Therefore, this architecture limits the integration capacity of DRAM memory cells. Any reduction in the dimensions of the cell should adhere to the alignment margins, which are inherent to the photolithography tools used. The size of the capacitance is thus limited by the two alignment tolerances required for the insertion of the bit line contact.
Therefore, unless improvements in the equipment enabling the alignment of the etching masks of one level with reference to another are considered, it is not possible to reduce any dimensions in the memory cell, and consequently, integration density will not be increased. Increasing integration density of DRAM cells is very important, particularly relating to embedded memories. Irrespective of the application, for an equivalent capacitance, it is important that the memory takes up as little space as possible on the chip on which it is embedded in order to integrate the maximum number of logic functions on the chip.
The drawback of the prior art architecture discussed above therefore hinders the development of DRAM applications given that they limit the integration density of the memory cells. Another disadvantage of the prior art architecture relates to the reliability of the application method. When the dimensions of the elec 2 grid are incorrect or when it is excessively offset, a recycling loop must be used before starting the etching step. Therefore, the architecture of the prior art results in limitations in terms of productivity and cycle time.
In view of the foregoing background, an object of the present invention is to provide a DRAM architecture which makes it possible to improve the integration density, and retain the same capacitance while making up for the drawbacks of the prior art.
This and other objects, advantages and features of the present invention are provided by the removal of the elec 2 grid in the insertion of the bit line contact, thus enabling the insertion to be avoided for new generations of photolithography equipment. The invention thus also represents a benefit in terms of cost reduction.
The DRAM cell architecture according to the invention makes it possible to do away with the alignment margin, which must normally be observed during the photoetching step of the upper electrode plate elec 2. To do this, the opening of the upper electrode elec 2 for the insertion of the bit line contact is self-defined with reference to the lower electrode elec 1 of the capacitance. The invention then makes it possible to carry out a self-alignment of elec 2 on elec 1, and thus carry out the etching of the opening in the upper electrode plate elec 2 without having to take any photos. This does away with the alignment constraints inherent to the positioning of the elec 2 grid with reference to the lower level.
Advantageously, the self-alignment of the removal of the upper electrode layer elec 2 on the lower electrode elec 1 is obtained by forming a difference in topography at the point where the opening of the upper electrode plate elec 2 is to be made for the insertion of the bit line contact.
Therefore, the invention relates to a DRAM memory integration method, where each memory cell, as defined by a bit line and a word line, comprises a storage capacitance and an access transistor. The method is characterized in that it comprises the following steps:
a) depositing a barrier layer followed by a silicon oxide layer;
b) photoetching the silicon oxide to define cylinders in which the capacitances are to be formed;
c) depositing a first polysilicon layer to form the lower electrode of the capacitances;
d) mechanical-chemical polishing to remove the polysilicon from the first layer between the capacitances;
e) removing part of the silicon oxide layer to create a difference in topography between each lower electrode and the silicon oxide layer;
f) depositing a dielectric layer;
g) depositing a second doped polysilicon layer to form a continuous upper electrode plate, the difference in topography being only retained in a zone where it is necessary to open the upper electrode plate to insert the bit line contact;
h) depositing a third non-doped polysilicon layer;
i) implanting dopants in the third non-doped polysilicon layer so as only to implant the upper part of the layer located in the zone showing the difference in the topography;
j) selective etching to only remove the part of the non-doped polysilicon layer located in the lower part of the zone; and
k) etching to remove the entire remainder of the third polysilicon layer and the part of the upper electrode layer located in the lower part, with the removal of the upper electrode layer being self-aligned on the lower electrode.